At the end of 2024, following the keynote speech at IEDM, 2D Field Effect Transistor  (2D FETs) and carbon nanotubes were highlighted as potential future technologies for logic processes. Since their proposal in 1998, CNT FETs have shown promise after more than a quarter of a century, thanks to significant advancements in controlling the nanotube diameters during manufacturing. However, I believe 2D FETs hold greater potential as the future of logic processes. This is not only due to the industry’s relentless efforts in R&D but also because of the academic community’s exhaustive exploration of 2D materials and their physical and chemical characterizations.

2D FETs utilize 2D materials—monolayer  consisting of single-atom-thick structures—as the channel material in field-effect transistors. In a typical FET, one side features a source electrode, which serves as the origin of signal carriers (electrons or holes) and exhibits metallic conduction. The central channel, traditionally made of silicon, is a semiconductor, while the drain electrode on the opposite side collects the carriers and also exhibits metallic conduction. Above the channel lies silicon dioxide, topped by the gate electrode, which is conductive. When a voltage exceeding the threshold voltage is applied to the gate, its electric field modulates the energy bandgap of the semiconductor below, enabling conduction. This allows carriers to flow from the source through the channel to the drain.

2D FETs represent a fundamental shift in the semiconductor industry by replacing silicon semiconductors with 2D semiconductor materials. Historically, silicon wafers were chosen primarily because silicon was the optimal channel semiconductor material. Today, the continued use of silicon as a substrate is largely due to the extensive engineering, manufacturing infrastructure, and intellectual property developed around it—an ecosystem so vast and deeply entrenched that it cannot be easily replaced.

Why 2D Semiconductor Materials?

The answer lies in addressing the Short Channel Effect (SCE), a challenge that arises as transistor scaling reduces the channel length, negatively impacting the intended functionality of FETs. This issue became evident as early as the 1980s, around the 1 μm process node. To put this in perspective, the covalent bond length of silicon is 0.234 μm, meaning 1 μm spans approximately 400 silicon atoms—still considered bulk material. However, IC design engineers began to observe issues such as drain-induced barrier lowering (DIBL), threshold voltage roll-off, and increased subthreshold leakage. Simply put, FETs became less controllable, with unintended leakage currents occurring before the set voltage threshold was reached.

By the 0.5 μm node, these problems intensified. Shorter channels introduced additional challenges like hot carrier injection, where carriers, energized by high electric fields between the source and drain, overcame material potential barriers and entered unintended regions such as the oxide layer above the channel, degrading device performance and reliability.

Early Solutions to SCE

Initial engineering solutions to SCE included lightly doped drains (LDD), refinements in gate oxide thickness, applying stress to the channel to enhance electron mobility, retrograde wells, halo implants, dual gate oxides, and shallow trench isolation (STI).

Modern Approaches

As scaling continued, the challenges grew more complex, leading to innovative approaches:

1. New Materials: For example, replacing conductive polysilicon with metallic titanium nitride (TiN) and using high-k dielectric materials like hafnium dioxide (HfO₂) instead of traditional silicon dioxide for the gate oxide layer.

2. New Structures: Structural innovations such as FinFETs (introduced at the 14 nm node) replaced traditional 2D planar FETs with 3D structures. These advancements have continued with GAA nanosheets (gate-all-around nanosheets) currently in production and future designs like CFETs (complementary FETs), which stack NFETs and PFETs vertically to save die space.

Beyond Scaling: A Paradigm Shift

Although these advancements are categorized as "More Moore" (as opposed to "Beyond Moore" advanced packaging), the creation of economic value now relies increasingly on new materials, device architectures, and physical mechanisms. This signifies a paradigm shift in semiconductor R&D competition, opening a new chapter where innovation extends beyond traditional scaling and engineering methods.

From  Digitimes